1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method. In particular, the present invention relates to a semiconductor device of reduced gate overlap capacitance and a method of manufacturing the semiconductor device.
2. Description of the Background Art
As the channel length of an MOS transistor is decreased with increasing the integration degree of semiconductor integrated circuits, it is increasingly difficult to reduce a gate overlap length in proportion to a gate length. As the result, the rate of gate overlap capacitance to intrinsic gate capacitance is greatly increased.
A reduction in parasitic capacitance, especially gate overlap capacitance, is the key to achieve high-speed operation of transistors at low power supply voltages.
As a technique of reducing gate overlap capacitance, there is one in which an already formed gate oxide film is further oxidized to increase the thickness of its edge portion. This technique is hereinafter referred to as “smile oxidation” (see for example the 22nd column and FIG. 9 in Japanese Patent Application Laid-Open No. 8-78684).
Specifically, the above-mentioned publication discloses the technique that with a gate electrode formed on a gate oxide film, thermal oxidation in a dry oxygen atmosphere containing neither vapor nor hydrogen is performed such that both ends of the gate oxide film is sharply thickened, thereby reducing gate overlap capacitance.
There is also other technique that with a gate electrode of polycrystal silicon (polysilicon) formed on a gate oxide film, thermal oxidation is performed to increase both ends of a gate oxide film at the same time that a thermal oxide film is formed on the surface of the gate electrode, although there is no description of a reduction in gate overlap capacitance (see for example the 16th column and FIG. 9 in Japanese Patent Application Laid-Open No. 7-335875, the fourth column and FIG. 2 in Japanese Patent Application Laid-Open No. 5-129595, and the fourth and fifth columns and FIG. 1D in Japanese Patent Application Laid-Open No. 2000-138183).
However, a reduction in gate overlap capacitance cannot be achieved only by increasing both ends of a gate oxide film and even a problem such as reduction in driving current may occur.